Chip scale package and method of fabricating the same

ABSTRACT

Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a chip scale package, and more particularly to a chip scale package which is miniaturized and more easily fabricated by forming conductive layers on both surfaces of a chip and by forming electrode surfaces on side surfaces of the conductive layers, and a method of fabricating the chip scale package.

[0003] 2. Description of the Related Art

[0004] Generally, semiconductor devices such as diodes are packaged and these packaged devices are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor device to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor device from external stresses, thereby improving reliability of the package.

[0005] In order to satisfy recent trends of miniaturization of semiconductor products, the semiconductor chip packages also have been miniaturized. Therefore, a chip scale package (also, referred to as a “Chip Size Package”) has been introduced.

[0006]FIG. 1 is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package 10 of FIG. 1 employs a ceramic substrate 1 and is a diode package with two terminals.

[0007] With reference to FIG. 1, two via holes, i.e., a first via hole 2 a and a second via hole 2 b, are formed on the ceramic substrate 1. The first and the second via holes 2 a and 2 b are filled with a conductive material so as to electrically connect the upper surface of the substrate 1 to the lower surface of the substrate 1. Then, a first and a second upper conductive lands 3 a and 3 b are formed on the upper surfaces of the first and the second via holes 2 a and 2 b, respectively. A first and a second lower conductive lands 4 a and 4 b are formed on the lower surfaces of the first and the second via holes 2 a and 2 b, respectively. The second upper conductive land 3 b is directly connected to a terminal formed on the lower surface of the diode 5, i.e., a mounting surface of the diode 5 on a printed circuit board, and the first upper conductive land 3 a is connected to the other terminal formed on the upper surface of the diode 5 by a wire 7. A molding part 9 using a conventional resin is formed on the upper surface of the ceramic substrate 1 including the diode 5 in order to protect the diode 5 from the external stresses. Thereby, the manufacture of the package 10 is completed.

[0008]FIG. 2 is a cross-sectional view of a conventional chip scale package assembly, in which the chip scale package is mounted on the printed circuit board.

[0009] As shown in FIG. 2, the manufactured diode package 10 is mounted on the printed circuit board 20 by a reflow soldering. That is, the diode package 10 is mounted on the printed circuit board 20 by arranging the lower conductive lands 4 a and 4 b of the package 10 on the corresponding signal patterns of the printed circuit board 20 and by then connecting the lower conductive lands 4 a and 4 b to the signal patterns of the printed circuit board 20 with a solder 15.

[0010] As shown in FIGS. 1 and 2, since the diode usually has a terminal on each of its two opposite surfaces, these terminals must be interconnected by wires. However, these wires require a large space on the upper surface of the chip, thereby increasing the overall height of the package. Further, since at least two via holes, corresponding to the number of terminals of the diode, must be formed on the ceramic substrate, an area as large as the total diameters of the via holes is further required. Moreover, in order not to connect the conductive lands formed on the upper and the lower surfaces of the via holes to each other, the conductive lands must be spaced from each other by a minimum interval. Therefore, the substrate has a large size so as to satisfy the aforementioned conditions, and the size of the substrate imposes a limit in miniaturizing the package.

[0011] Further, the ceramic substrate which is employed by the above-described package is high-priced, thereby increasing the production cost of the package. Moreover, the conventional fabrication process of the package requires a wire-bonding step and a molding step as well as a die-bonding step, thereby being very complicated.

[0012] Accordingly, a packaging technique, which can minimize the size of the package and simplify its fabricating process, has been demanded.

SUMMARY OF THE INVENTION

[0013] Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a chip scale package, which is miniaturized and more simply fabricated, by forming conductive layers on an upper and a lower surfaces of a chip with terminals and by forming electrode surfaces on side surfaces of the conductive layers, thereby improving the reliability of the package.

[0014] It is another object of the present invention to provide a chip package assembly with an innovative mounting method according to the structure of the chip scale package.

[0015] It is a yet another object of the present invention to provide a method of fabricating the chip scale package.

[0016] In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a chip scale package comprising a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface, a first and a second conductive layers formed on the first and the second surfaces of the chip, respectively, and electrode surfaces, each formed on side surfaces of the first and the second conductive layers.

[0017] In accordance with another aspect of the present invention, there is provided a chip scale package assembly comprising a chip scale package and a printed circuit board. The chip scale package comprises a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface, a first and a second conductive layers formed on the first and the second surface of the chip, respectively, and electrode surfaces, each formed on side surfaces of the first and the second conductive layers. The printed circuit board comprises connection pads for being connected to the electrode surfaces of the chip scale package, and circuit patterns connected to the connection pads.

[0018] In accordance with yet another aspect of the present invention, there is provided a method of fabricating a chip scale package, comprising the steps of (i) preparing a wafer including a plurality of chips, the chip including a terminal on its upper and its lower surfaces, respectively, (ii) forming conductive layers, each formed on the upper and the lower surfaces of the wafer, and (iii) dicing the wafer into package units, each package unit including a chip, and forming electrode surfaces, each formed on side surfaces of two conductive layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020]FIG. 1 is a schematic cross-sectional view of a conventional chip scale package;

[0021]FIG. 2 is a cross-sectional view of a conventional chip scale package assembly, in which the chip scale package is mounted on a printed circuit board;

[0022]FIG. 3 is a perspective view of a chip scale package in accordance with a preferred embodiment of the present invention;

[0023]FIG. 4 is a perspective view of a chip scale package assembly, in which a chip scale package is mounted on a printed circuit board in accordance with the preferred embodiment of the present invention; and

[0024]FIGS. 5a through 5 f are cross-sectional views illustrating each step of a method of fabricating the chip scale package in accordance with a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Now, preferred embodiments of the present invention will be described in detail with reference to the annexed drawings.

[0026]FIG. 3 is a perspective view of a chip scale package in accordance with a preferred embodiment of the present invention.

[0027] With reference to FIG. 3, a chip scale package 30 comprises a chip 35, an upper conductive layer 31 a formed on the upper surface of the chip 35, a lower conductive layer 31 b formed on the lower surface of the chip 35, a first electrode surface 33 a formed on one side surface of the upper conductive layer 31 a, and a second electrode surface 33 b formed on one side surface of the lower conductive layer 31 b. Herein, the side surface of the upper conductive layer 31 a having the first electrode surface 33 a and the side surface of the lower conductive layer 31 b having the second electrode surface 33 b are on the same side surface of the conductive layers 31 a and 31 b. The chip 35 includes an upper terminal (not shown) formed on the upper surface and a lower terminal (not shown) formed on the lower surface. For example, the chip 35 is a diode.

[0028] The upper conductive layer 31 a formed on the upper surface of the chip 35 is connected to the upper terminal (not shown), and the lower conductive layer 31 b formed on the lower surface of the chip 35 is connected to the lower terminal (not shown). The upper and the lower conductive layers 31 a and 31 b may be a metal layer made of copper (Cu), but is not limited thereto. The upper and the lower conductive layers 31 a and 31 b must have a designated depth according to an interval between connection pads formed on a printed circuit board. That is, since the electrode surfaces 33 a and 33 b formed on the side surfaces of the upper and the lower conductive layers 31 a and 31 b are located on the corresponding connection pads of the printed circuit board, the upper and the lower conductive layers 31 a and 31 b require a sufficient thickness.

[0029] The upper and the lower conductive layers 31 a and 31 b can be formed at a predetermined depth by a conventional plating process. However, the formation of the upper and the lower conductive layers 31 a and 31 b using the plating process requires a long time and incurs a higher production cost. Therefore, preferably, a plating layer is first formed by electroplating. Then at least one copper layer is stacked on the plating layer, thereby easily forming the conductive layers with the desired depth.

[0030] Further, the first electrode surface 33 a is formed on one side surface of the upper conductive layer 31 a, and the second electrode surface 33 b is formed on one side surface of the lower conductive layer 31 b. The side surface of the upper conductive layer 31 a having the first electrode surface 33 a and the side surface of the lower conductive layer 31 b having the second electrode surface 33 b are on the same side surface of the upper and the lower conductive layer 31 a and 31 b. The first and the second electrode surfaces 33 a and 33 b are electrically and mechanically connected to the corresponding connection pads of the printed circuit board. Therefore, preferably, the first and the second electrode surfaces 33 a and 33 b are metal layers including gold (Au) so as to subsequently perform the soldering.

[0031] In the aforementioned chip scale package 30, the upper and the lower terminals (not shown) formed on the upper and the lower surfaces of the chip 35 are connected to the first and the second electrode surfaces 33 a and 33 b through the upper and the lower conductive layers 31 a and 31 b, respectively. Therefore, the side surfaces having the first and the second electrode surfaces 33 a ad 33 b are mounting surfaces on the printed circuit board. That is, the chip scale package 30 of FIG. 3 is turned at an angle of 90 degrees, and the turned chip scale package 30 is then mounted on the printed circuit board so that the first and the second electrode surfaces 33 a ad 33 b are connected to the corresponding connection pads of the printed circuit board.

[0032] In order to prevent the upper and the lower conductive layers 31 a and 31 b, which are exposed to the outside, from oxidizing, a passivation layer 37 may be formed on the upper and the lower conductive layers 31 a and 31 b except for the first and the second electrode surfaces 33 a and 33 b. Preferably, the passivation layer 37 is an insulation film formed by coating an insulating resin. If necessary, the passivation layer 37 may be further formed on the exposed side surfaces of the chip 35.

[0033]FIG. 4 is a perspective view of a chip scale package assembly 70, in which a chip scale package 40 is mounted on a printed circuit board 51 in accordance with the preferred embodiment of the present invention.

[0034] As shown in FIG. 4, the chip package assembly 70 comprises the chip scale package 40 and the printed circuit board 51 for mounting the chip scale package 40. The chip scale package 40 comprises a chip 45, an upper conductive layer 41 a formed on the upper surface of the chip 45, a lower conductive layer 41 b formed on the lower surface of the chip 45, a first electrode surface 43 a formed on one side surface of the upper conductive layer 41 a, and a second electrode surface 43 b formed on one side surface of the lower conductive layer 41 b. Herein, the side surface of the upper conductive layer 41 a having the first electrode surface 43 a and the side surface of the lower conductive layer 41 b having the second electrode surface 43 b are on the same side surfaces of the upper and the lower conductive layers 41 a and 41 b. The first and the second electrode surfaces 43 a and 43 b are mounting surfaces of the chip scale package 40 on the printed circuit board 51. The first and the second electrode surfaces 43 a and 43 b are connected to the upper and the lower terminals (not shown) of the chip 45 through the upper and the lower conductive layers 41 a and 41 b, respectively. The chip scale package 40 is mounted on the printed circuit board 51 by disposing the first and the second electrode surfaces 43 a and 43 b of the chip scale package 40 on corresponding connection pads 53 a and 53 b of the printed circuit board 51 and by performing the soldering between the first and the second electrode surfaces 43 a and 43 b and the connection pads 53 a and 53 b, thereby completing the fabrication of the chip package assembly 70 of FIG. 4.

[0035] Designated circuits (not shown) formed on the printed circuit board 51 are connected to each terminal of the chip 45 via the first and the second electrode surfaces 43 a and 43 b of the chip scale package 40 connected to the connection pads 53 a and 53 b. As described above, the first and the second conductive layers 41 a and 41 b have a designated depth according to the interval between the connection pads 53 a and 53 b of the printed circuit board 51.

[0036] Further, the present invention provides a method of fabricating the chip scale package. FIGS. 5a through 5 f are cross-sectional views illustrating each step of the method of fabricating the chip scale package in accordance with the preferred embodiment of the present invention.

[0037] First, as shown in FIG. 5a, a wafer 125 including a plurality of chips is prepared. A terminal is formed on the upper and the lower surfaces of each chip. Herein, each chip is divided by a dotted line of the upper surface of the wafer 125. FIG. 5a shows a partial cross-section of the wafer 125. However, the whole structure of the wafer 125 with a plurality of the chips will be apparent to those skilled in the art.

[0038] The chip comprises an upper and a lower terminals 101 a and 101 b on its upper and lower surfaces, respectively. Further, a mask pattern 118 with a plurality of windows is formed on the wafer 125, thereby exposing terminal areas of the wafer 125. The windows of the mask pattern 118 correspond to the terminal areas of the wafer 125.

[0039] As shown in FIG. 5b, upper and lower conductive layers 121 a and 121 b are formed on the upper and the lower surfaces of the wafer 125, respectively. Then, passivation layers 127 a and 127 b are formed on the first and the lower conductive layers 121 a and 121 b, respectively.

[0040] The upper and the lower conductive layers 121 a and 121 b are connected to the upper and the lower terminals 101 a and 101 b, respectively. The upper and the lower conductive layers 121 a and 121 b may be formed by the plating step. However, preferably, the upper and the lower conductive layers 121 a and 121 b are formed by forming a plating layer and then by stacking at least one copper layer on the plating layer, thereby having a depth corresponding to the interval between the connection pads of the printed circuit board.

[0041] The passivation layers 127 a and 127 b prevent the upper and the lower conductive layers 121 a and 121 b from oxidizing, thereby improving the reliability of the package. Preferably, the upper and the lower conductive layers 121 a and 121 b are insulation layers formed by coating an insulation resin. In case the wafer 125 can be sufficiently protected from the external stresses only using the naturally formed oxidation layer according to the usage condition of the chip scale package, the passivation layers 127 a and 127 b may be omitted. Further, the step of forming the passivation layers 127 a and 127 b may be variously applied. That is, as shown in FIG. 5f, which will be described later, after a dicing step, the passivation may be collectively formed on the upper, the lower, and the side surfaces of the conductive layers. However, considering on the oxidation of the conductive layers or an attachment of one surface of the wafer to a tape during the dicing step, the passivation layers 127 a and 127 b are preferably formed at this step.

[0042] As shown in FIG. 5c, the wafer is first-diced so as to form one side surface of the chip scale package. Preferably, the wafer is diced along the scribe lines into two rows. In the first-diced wafer 130′ including two chip scale packages, only one side surface of each chip scale package is exposed to the outside.

[0043] As shown in FIG. 5d, first and second electrode layers 133 a and 133 b are formed on the side surfaces of the upper and the lower conductive layers 121 a and 121 b of the diced wafer 130′, respectively. The first and the second electrode surfaces 133 a and 133 b are connected to each terminal of the chip through the first and the second conductive layers 121 a and 121 b. The first and the second electrode surfaces 133 a and 133 b are formed by the plating process using gold (Au). Thereby, the electrode surface is not formed on the side surfaces of the chip made of silicon and the passivation layer made of insulating resin, but is formed on the side surfaces of the first and the second conductive layers 121 a and 121 b made of metal. That is, the first and the second electrode surfaces 133 a and 133 b are selectively formed on the wafer.

[0044] After forming the first and the second electrode surfaces 133 a and 133 b, as shown in FIG. 5e, the first-diced wafer 130′ is then second-diced, thereby forming a plurality of chip scale package units 130″. Then, as shown in FIG. 5f, a passivation layer 137 is formed on the side surfaces of the first and the second conductive layers 121 a and 121 b, thereby completing the fabrication of a chip scale package 140, as shown in FIG. 3. The passivation layer 137 shown in FIG. 5f is formed in the same manner as the passivation layers 127 a and 127 b shown in FIG. 5b. That is, the passivation layer 137 shown in FIG. 5f is also formed by coating insulating rein.

[0045] The method of fabricating the chip scale package shown in FIGS. 5a through 5 f is a preferred embodiment of the present invention. Therefore, the method of fabricating the chip scale package may be variously modified within the scope and spirit of the present invention. Particularly, the steps shown in FIGS. 5c through 5 f can be widely modified according to the dicing steps. That is, after first-dicing the wafer so that side surfaces other than a designated side surface of the chip scale package are formed, a passivation layer is formed on side surfaces of conductive layers forming the side surface obtained by the first-dicing step, respectively. Then, the first-diced wafer is second-diced, thereby forming chip scale package units. An electrode surface is formed on the side surfaces the conductive layers forming the side surface obtained by the second-dicing step, respectively. However, as described above, the wafer is attached and fixed to the tape prior to the dicing step. In this case, as larger sized wafer is attached to the tape, the fabrication process is more stably performed. Therefore, preferably, a large area of the first-diced wafer is fixed to the tape. Therefore, the aforementioned steps shown in FIGS. 5c to 5 f are preferable.

[0046] In accordance with the method of fabricating the chip scale package of the present invention, the wafer is diced into a plurality of chip scale packages having one chip, and the electrode surfaces are formed on the side surfaces of two conductive layers of one side surface of the chip scale package and the passivation layers are formed on other side surfaces of the conductive layers. Therefore, each dicing step for forming the side surfaces of the chip scale package and the steps for forming the passivation layers and the electrode surfaces may be variously modified in order and manner. These modifications or improvements are within the scope and sprit of the present invention.

[0047] As apparent from the above description, the present invention provides a chip scale package, which is miniaturized and more easily fabricated, by forming conductive layers on upper and lower surfaces of a chip, each having a terminal and by forming electrode surfaces on the same sides surface of the conductive layers, thereby improving the reliability of the package. Further, the present invention provides a method for fabricating the chip scale package, in which the conventional wire bonding step or via hole forming step are omitted, thereby simplifying the fabrication process and reducing the fabrication cost.

[0048] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. 

What is claimed is:
 1. A chip scale package comprising: a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface; a first and a second conductive layers formed on the first and the second surfaces of the chip, respectively; and electrode surfaces formed on each of designated side surfaces of the first and the second conductive layers.
 2. The chip scale package as set forth in claim 1, further comprising passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.
 3. The chip scale package as set forth in claim 2, wherein said passivation layers are made of insulating films formed by coating insulation resin.
 4. The chip scale package as set forth in claim 1, wherein the side surface of the chip and the side surfaces of the first and the second conductive layers form one flat surface.
 5. The chip scale package as set forth in claim 1, wherein the conductive layers are metal layers including copper (Cu).
 6. The chip scale package as set forth in claim 1, wherein the electrode surfaces are metal layers including gold (Au).
 7. The chip scale package as set forth in claim 1, wherein each of the first and the second conductive layers comprises a plating layer formed on the first and the second surfaces of the chip, and at least one copper layer stacked on the plating layer.
 8. The chip scale package as set forth in claim 1, wherein the chip is a diode.
 9. A chip scale package assembly comprising: a chip scale package comprising: a chip having a first surface provided with a first terminal and a second surface provided with a second terminal, the second surface being opposite to the first surface; a first and a second conductive layers formed on the first and the second surface of the chip, respectively; and electrode surfaces formed on each of designated side surfaces of the first and the second conductive layers; and a printed circuit board comprising: connection pads for being connected to the electrode surfaces of the chip scale package; and circuit patterns connected to the connection pads.
 10. The chip scale package assembly as set forth in claim 9, further comprising passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.
 11. The chip scale package assembly as set forth in claim 10, wherein said passivation layers are made of insulating films formed by coating insulation resin.
 12. The chip scale package assembly as set forth in claim 9, wherein the conductive layers are metal layers including copper (Cu).
 13. The chip scale package assembly as set forth in claim 9, wherein the electrode surfaces are metal layers including gold (Au).
 14. The chip scale package assembly as set forth in claim 9, wherein each of the first and the second conductive layers comprises a plating layer formed on the first and the second surfaces of the chip, and at least one copper layer stacked on the plating layer.
 15. The chip scale package assembly as set forth in claim 9, wherein the chip is a diode.
 16. A method of fabricating a chip scale package, said method comprising the steps of: (i) preparing a wafer including a plurality of chips, said chip including a terminal on each of its upper and its lower surfaces, respectively; (ii) forming conductive layers, each formed on the upper and the lower surfaces of the wafer; and (iii) dicing the wafer into package units, each package unit including a chip, followed by forming electrode surfaces formed each of designated side surfaces of the conductive layers.
 17. The method of fabricating the chip scale package as set forth in claim 16, wherein the step (iii) further comprises the step of forming passivation layers, each formed on the exposed surfaces of the first and the second conductive layers except for the side surfaces having the electrode surfaces.
 18. The method of fabricating the chip scale package as set forth in claim 17, wherein said passivation layers are made of insulating films formed by coating insulation resin.
 19. The method of fabricating the chip scale package as set forth in claim 16, after the step (ii), further comprising the step of forming passivation layers, each formed on the first and the second conductive layers except for the side surfaces having the electrode surfaces, wherein the step (iii) comprises the sub-steps of: first-dicing the wafer so that one side surface of the chip scale package is formed; forming electrode surfaces on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by first-dicing the wafer; second-dicing the wafer into package units; and forming passivation layers on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by second-dicing the wafer.
 20. The method of fabricating the chip scale package as set forth in claim 19, wherein the step of first-dicing the wafer is the step of dicing the wafer so that scribe lines of the wafer are cut into two rows.
 21. The method of fabricating the chip scale package as set forth in claim 16, wherein the step (iii) comprises the sub-steps of: first-dicing the wafer so that one side surface of the chip scale package is formed; forming passivation layers on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface of the chip scale package obtained by first-dicing the wafer; second-dicing the wafer into package units; and forming electrode surfaces on side surfaces of the first and the second conductive layers, said side surfaces formed on the side surface obtained by second-dicing the wafer.
 22. The method of fabricating the chip scale package as set forth in claim 21, wherein in the step of first-dicing, the wafer is diced into two package units.
 23. The method of fabricating the chip scale package as set forth in claim 16, wherein the conductive layers are formed by a plating method.
 24. The method of fabricating the chip scale package as set forth in claim 16, wherein the conductive layers are metal layers including copper (Cu).
 25. The method of fabricating the chip scale package as set forth in claim 16, wherein the electrode surfaces are metal layers including gold (Au).
 26. The method of fabricating the chip scale package as set forth in claim 16, wherein the conductive layers are formed by forming metal layers by a plating method and by stacking at least one copper layer on each metal layer.
 27. The method of fabricating the chip scale package as set forth in claim 16, wherein the electrode surfaces are formed by a plating method.
 28. The method of fabricating the chip scale package as set forth in claim 16, wherein the chip is a diode. 